1. Field
Example embodiments relate to a vertical type semiconductor device, a method of manufacturing a vertical type semiconductor device and method of operating a vertical type semiconductor device. More particularly, example embodiments relate to a vertical type semiconductor device having a single transistor, a method of manufacturing a vertical type semiconductor device having a single transistor and method of operating a vertical type semiconductor device having a single transistor.
2. Description of the Related Art
Generally, a DRAM (dynamic random access memory) device includes a unit cell requiring one transistor and one capacitor per bit. The DRAM device stores data using the capacitor which may be charged or un-charged. The DRAM device loses data stored in each cell when power is not supplied. Because capacitors leak charge, the data eventually fades unless the capacitor charge is refreshed periodically.
Capacitance of the capacitor may be increased in order to increase the refresh period. Because the capacitance is proportional to physical size of the capacitor, integrating the DRAM device in higher density may be difficult.
Accordingly, a 1T DRAM which may be a capacitorless bit cell design has been developed. The 1T DRAM has a structure in which a transistor may be formed on a surface of a floating body. The 1T DRAM stores data by storing or erasing a charge in the floating body. Also, the 1T DRAM reads the stored data using a detectable shift in the threshold voltage of the transistor caused by stored charges in the floating body.
However, the shift in the threshold voltage of the transistor caused by stored charges may be smaller. As a result, when data stored in the transistor is read, errors caused from a read sensing margin may occur. Also, power consumption becomes larger because of frequent refresh operations.